Typical dynamic random access memories (DRAMs) are generally asynchronous devices whose operation are controlled in large part by the row access signals (RAS) and column address signals (CAS).
Synchronous dynamic random access memories (SDRAMs) are designed to operate in a synchronous memory system. As such, the input and output signals, with the possible exception of clock enable during Power Down and Self Refresh modes, are synchronized to the edge of the system clock. Synchronous DRAMs provide substantial advantages in dynamic memory operating performance. One key advancement of the synchronous DRAM is its ability to synchronously burst data at a high-speed data rate. Additionally, synchronous DRAMs come with programmable features, such as a programmable READ latency period. Programmable READ latencies of one, two or three clocks are typical. The READ latency determines at which clock cycle the data will be available after a READ Command is initiated, regardless of the clock rate (tCK). Depending on the frequency, data can be made available on the output at a point up to one clock cycle less than the READ latency. For example, a programmed READ latency of two clock cycles with a cycle period which is greater than the minimum access time from the READ Command (tAA) will provide data almost immediately after the first clock cycle, but the data will remain valid until after the second clock cycle because of the programmed READ latency of two clock cycles.
The programmable READ latency enables the synchronous DRAM to be efficiently utilized in different memory systems having different system clock frequencies. For example, if the synchronous DRAM has a minimum access time (tAA) of 37 ns and the system clock cycle, tCK, is 15 ns (66 Mhz), a READ latency of three clock cycles will provide the first valid data-out between the second clock cycle (30 ns) and the third clock cycle (45 ns) from the READ Command. The data remains valid until after the third clock cycle (the READ latency period). However, if the tCK for the memory system is 25 ns (40 Mhz), the programmer of the synchronous DRAM may find some time benefits in setting the READ latency to two. If the READ latency is set at two, the first valid data-out will occur between the first clock cycle (25 ns) and the second clock cycle (50 ns) from the READ Command. The data remains valid until after the second clock cycle (the READ latency period), but if the READ latency were programmed at three, the valid data-out would remain until after the third clock cycle (75 ns) which would be an inefficient use of time.
Standard synchronous DRAMs latch and decode the row address when Row Address Strobe is fired via an Active Command and then will latch and decode the column address when Column Address Strobe is fired via the READ/WRITE Command. The two critical parameters are tRCD (Active Command to READ/WRITE Command) and the tAA (READ/WRITE Command to data-out). Synchronous DRAMs utilizing a pipelined architecture have been used with tAA and tRCD to have similar performance. Depending on the system clock frequency, typical synchronous DRAMs allocate three system clock cycles each for tRCD and tAA. For a lower system clock frequency, tRCD and tAA can be set at two system clock cycles each. As such, the total memory access time is 6 clock cycles and 4 clock cycles, respectively. A need always exists for minimizing the time required for a memory access, and if either tRCD and tAA can be reduced without affecting system operation, the memory access time of the system can be reduced.
Accordingly, there is a need for a device for optimizing the speed path for DRAMs with programmable READ latencies which minimizes the time requirements for a memory access.